Semiconductor chip carrier

ABSTRACT

A circuit unit such as performing the function of a chip carrier. In one example, it is in the form of a thin square of insulating material having contact pads arranged side by side along the four edges of both major surfaces. The chip is secured substantially centrally of the insulating material and connections are made from it to the contacts on both of the major surfaces. The carrier has a lower insulating layer (5) having contacts (6) extending over its under surface and carrying the chip (14) on its upper surface. An insulating spacer (8) carries further contacts (12). Electrical connections (16 and 18) are made to the contacts (6 and 12). An insulating cover (not shown) then closes off the hollow interior, locating on a shoulder (10). The contacts (12) thus provide the contacts on the upper surface of the finished construction. A single layer construction is also disclosed. Double-sided chip carriers formed in this way are particularly suited for side-by-side mounting in racked manner, enabling maximum use to be made of the contacts on both of the major surfaces and facilitating flow of cooling air.

The invention relates to electrical circuit units.

Embodiments of the invention to be described in more detail below are inthe form of so-called "chip carriers", that is circuit unitsincorporating integrated circuits ("chips"). Such embodiments of theinvention may be used, for example, in circuit assemblies disclosed inco-pending U.K. Patent Application No. 8203852 (Ser. No. 2095039).

According to the invention, there is provided an electrical circuitunit, comprising electrically insulating material providing twoside-by-side major surfaces each surface carrying a plurality ofseparate electrical contacts arranged adjacent to the edges of thesurface, and electrical connections carried by the insulating materialand connected to the contacts.

According to the invention, there is also provided a chip carrier,comprising flat electrically insulating material of rectangular externalconfiguration defining upper and lower major surfaces, a plurality ofseparate electrical contacts arranged side by side along the four sidesof each of the two major surfaces, a chip carried by the insulatingmaterial and completely enclosed, and electrical connections between thechip and the contacts.

Electrical circuit units embodying the invention will now be describedby way of example only and with reference to the accompanyingdiagramatic drawings in which:

FIG. 1 is a perspective view of one of the circuit elements with a topinsulating layer removed;

FIG. 2A is a plan view of a bottom insulating layer of the unit of FIG.1;

FIG. 2B is a side view of the layer of FIG. 2A;

FIG. 3A is a plan view of an insulating spacer forming part of the unitof FIG. 1;

FIG. 3B is a side view of the spacer of FIG. 3B;

FIG. 4 is a plan view of the insulating top layer for the unit of FIG. 1and which is omitted from FIG. 1;

FIG. 5 is a perspective view of the unit of FIG. 1 with the topinsulating layer in position;

FIG. 6 is a perspective view showing one of the circuit units and, inexploded form, part of a racking assembly;

FIG. 7 is an end view of two of the circuit units connected by a spacerelement;

FIG. 8 is a side view of an alternative spacer element;

FIG. 9 corresponds to FIG. 7 but shows the spacer element of FIG. 8 inuse;

FIG. 10 is a plan view corresponding to FIG. 5 but showing a modifiedform of the unit of FIG. 1;

FIG. 11 is a perspective view of another form of the circuit unit;

FIG. 12 is a plan view of a modified form of the circuit unit of FIG.11;

FIG. 13 shows chips mounted on a tape in a tape-automated-bondingsystem; and

FIGS. 14 and 15 show stages in transferring chips from the tape shown inFIG. 13 to the chip carrier of FIG. 12.

The unit comprises a base made of suitable insulating material such asglass fibre insulating material or ceramic material for example whichmay be square. Along each edge three (in this example) conductive padsor contacts 6 are provided. These are made of strip material such asplated on, and, as shown in FIGS. 1, 2A and 2B, each of them extendsaround an outside edge of the base so as to provide interconnectedcontact pads on the upper and lower surfaces of the base.

A spacer 8 of insulating material similar to that referred to above isplaced on top of the base 5 and matches its outside dimension. As shownparticularly in FIG. 1, the spacer has a shoulder 10 running around itsinside. Along each of the four edges of the spacer 8 three contacts 12are provided, each one of which extends on the outside surface of thespacer, over its top surface and terminates at the edge of the shoulder10.

An electrical circuit device may be placed within the circuit unit as sofar described.

In this particular example, the circuit device is an integrated circuitor chip 14 which is secured in a suitable manner to the upper surface ofthe base 5. Electrical connections such as shown at 16 and 18 are madefrom various points on the chip 14 to particular ones of the contacts 6and 12. Such connections may be made by wire-bonding or otherwell-established connection techniques. The connections 16 are made tothe contacts 6, that is, the contacts on the base 5, while theconnections 18 are made to the contacts 12, that is, the contacts of thespacer 8.

The circuit unit is then completed by means of an insulating top layer20 (FIG. 4), again such as made of the material described above forexample, which is sized and shaped so as to fit within the recessprovided by the shoulder 10 in the spacer 8. The top layer 20 thus sealsthe unit and protects the chip 14 and the internal connections 16 and18, the layer 20 being secured in position by means of adhesive. FIG. 5therefore shows the finished unit. It will be apparent that the finishedunit provides a chip carrier having contact pads on both of its twomajor surfaces. As such, it is particularly suitable for incorporationas an element within a slotted holder such as a circuit assembly of thetype disclosed in co-pending U.K. Patent Application No. 8203862 (Ser.No. 2095039). In such a circuit assembly, chip carriers such asdisclosed in the present Specification may be mounted side-by-side inracked fashion, fitting into a mounting structure which both supportsthem and makes electrical contact to the contacts on both major surfacesof the chip carriers. There is thus very effective use of space and goodcooling, among other advantages.

FIG. 6 shows chip carriers 21 as described above (but with five insteadof three contacts along each side) mounted side by side and also showstwo sides 22 of a racking assembly which has contacts 23 for makingconnections with the contacts 6 and 12. Each side 22 has a throughaperture 24 to aid cooling. The other two sides of the racking assemblyare omitted for clarity. In use all four sides would be clamped togetherto hold the chip carriers side by side and to make contact with them.

Instead, however, the chip carriers described could be used inconjunction with spacing elements placed between them, by means of whichthey would be electrically interconnected.

Such an arrangement is shown in FIG. 7 where two chip carriers are shownat 25, interconnected by a spacing element 26 made of suitableinsulating material having a hollow centre aperture 27 across whichconnections 28 extend to make connections between the contacts on thechip carriers.

An alternative arrangement is shown in FIGS. 8 and 9. There the spacerelement 26 is in the form of a hollow square frame through whose edgesthe connections 28 extend and are soldered to the contacts 6 and 12.

It will be apparent that the chip carrier described is advantageous inthat the arrangement of the contacts on both of its opposite surfacesmakes maximum use of the available space for external contacts ascompared with chip carriers which are designed to be mounted in a2-dimensional manner, that is, flat on a circuit board and whichtherefore can only have contacts on one of the two major surfaces. Thechip carriers described and illustrated herein can therefore be made ofreduced size in proportion to the number of contacts.

FIG. 10 shows a variation in which the base 5 and the spacer 8 (FIG. 1)are arranged to provide lugs 29 at the corners of the finished circuitunit to facilitate correct location and alignment of the circuit unitand its contacts 6 and 12 when used in a rack arrangement or similar.

The spacer 8 could be made of resilient insulating material which wouldthus help to provide increased contact pressure for the contacts 6 and12 when the unit is inserted in a suitable slotted holder.Advantageously the contacts 6 and 12 are arranged to stand slightlyproud from the upper and lower surfaces of the circuit unit.

Cooling may be improved by arranging for the material of the base 5and/or the spacer 8 and/or the top layer 20 to be made of heatdissipating material.

It will be appreciated that the circuit unit described is not restrictedto use as a chip carrier. Any suitable circuit device may beincorporated within the unit instead of an integrated circuit chip, andelectrical connections made to the contacts in the manner shown. Forexample, the circuit device incorporated could be a rechargeable ornonrechargeable cell or battery. Instead, however, there may be noactual circuit device within the unit. There could for example simply bean arrangement for interconnecting various ones of the contacts 6 and 12together by means of electrical connections which, when the top layer 20is in place, would be sealed-in and protected. Such a circuit unit wouldthen provide an interconnection unit for making predetermined crossoverconnections. Thus, in a racking arrangement in which a plurality ofcircuit units as described were arranged side-by-side in racked mannerin an assembly arranged to make electrical connections to the contacts 6and 12 (such as an assembly described in the above-mentioned co-pendingU.K. Patent Application) one of the racked units could be aninterconnection unit as just described, and if the other units on eitherside of it were carrying chips, for example, the interconnection unitwould provide a predetermined pattern of interconnections which, via thecontacts 6 and 12 of all three units, would make the requiredinterconnections between different parts of the chips in the adjacentchip carriers.

FIG. 11 shows another one of the circuit units which differs from theunit of FIG. 1 in that it is made of a single layer, 30, of insulatingmaterial instead of the three layers 5,8 and 20 of the unit of FIG. 1.As shown in FIG. 11, the single layer 30 of insulating material (whichmay be of the material described above for example) has contact pads 32plated to its upper surface along its four sides and contacts 34similarly plated to its under surface. On the upper surface, a circuitelement 36, which may again be an integrated circuit or chip (but couldbe any other suitable form of circuit device) is placed and bonded tothe layer 30 in a suitable manner. If desired, the circuit device 36could be placed within a suitably shaped recess.

Connections 38 connect various parts of the circuit device 36 to theupper contacts 32, such as by a wire bonding process of normal form.

Connections 40 similarly connect the circuit device 36 to the lowercontacts 34. The connections 40 are made to intermediate contact pads 42on the upper surface of the layer 30, these being in turn connected torespective ones of the contacts 34 via plated-through holes 44. However,other means of making connections through the layer 30 to the contacts34 could be used instead.

After the connections have been made, the circuit device 36 may beencapsulated in any suitable way by applying an encapsulant over it.

The single layer form showing in FIG. 11 is particularly suited for usewith tape-automated bonding systems.

FIGS. 12 to 14 show a modified form of the circuit of FIG. 11 andillustrate how a circuit device may then be placed in position thereonby means of a tape-automated-bonding system.

FIG. 12 illustrates the circuit unit which is similar to that shown inFIG. 11 except that it does not have the contact pads 42 and theplated-through holes 44, and has its centre removed to provide anopening 50. The contacts 34 are of course not visible in FIG. 8.

FIG. 13 shows a series of chips 36 mounted on leads 52 in openings 54 ina tape 56 in the normal tape-automated-bonding manner.

In the usual way, the tape 56 is indexed over the chip carrier and whenone of the chips 36 carried by the tape 56 is positioned over theopening 50 (FIG. 12), the chip is removed from of the tape 56 and on tothe chip carrier as shown in FIG. 14, the leads 52 becoming bonded toappropriate ones of the contacts 32 to make the required electricalconnections.

FIG. 15 shows the reverse side of the chip carrier with bonding pads 58on the underside of the chip 36. By means of these pads, the chip iselectrically connected to appropriate ones of the contacts 34 by wireconnections 60.

The chip is then encapsulated in a suitable encapsulant material.

The arrangement described in FIGS. 12 to 15 is advantageous in that itprovides even better cooling.

It may be advantageous to make the insulating material 30 in multilayerform with conductive layers between the insulating layers to provide acapacitive effect, the conductive layers being suitably electricallyconnected to particular ones of the contacts 6, 12.

The circuit units may be of any suitable size and can ha any suitablenumber of contacts. For example a circuit unit of square configurationand having sides of 37 millimeters (one and half inches) could have tenor eleven contacts per edge at a pitch of 2.5 millimeters (0.1 inches)or twice that number of contacts at half the pitch. Although the circuitunits are of square configuration, this is not essential. They could beof any other suitable configuration.

We claim:
 1. A chip carrier comprising:a body of flat electricallyinsulating material of rectangular external configuration defining upperand lower major surfaces; a first plurality of electrical contactsarranged side-by-side along the four sides of the upper surface and asecond plurality of electrical contacts arranged side-by-side along thefour sides of the lower surface, the contacts of the first pluralitybeing separate from the contacts of the second plurality; a single chipmounted on the insulating material and completely enclosed; andelectrical connections between the chip and the contacts, the body ofinsulating material being a single square slab of insulating materialhaving the chip mounted on the upper surface, the chip being enclosed byencapsulation.
 2. A chip carrier according to claim 1, characterised inthat the chip is connected to the contacts on the lower surface of theslab by means of plated-through holes extending through the slab.
 3. Achip carrier according to claim 1, characterised in that the slab ofinsulating material has an opening through it of greater size than thechip, the chip being mounted within the opening and supported therein bymeans of at least some of the said connections.
 4. A chip carriercomprising:a body of flat electrically insulating material ofrectangular external configuration defining upper and lower majorsurfaces; a first plurality of electrical contacts arranged side-by-sidealong the four sides of the upper surface and a second plurality ofelectrical contacts arranged side-by-side along the four sides of thelower surface, the contacts of the first plurality being separate fromthe contacts of the second plurality; a single chip mounted on theinsulating material and completely enclosed; and electrical connectionsbetween the chip and the contacts, the body of insulating materialincluding a square unitary base slab of insulating material havingopposed major surfaces one of which defines the lower surface and theother of which defines an intermediate surface, and having the secondplurality of the contacts arranged along the four edges of the lowersurface but each having an extension onto the intermediate surface, asquare hollow frame-shaped spacer of insulating material matching thesize of the base slab and defining frame-shaped top and under faces andhaving the first plurality of the contacts arranged on its top face, thespacer being mounted with its under face on the intermediate surface ofthe base slab so as to define an enclosure with that intermediatesurface and in which enclosure the chip is mounted, the spacer beingsized so that the extensions of the contacts on the base slab extendinto the enclosure, and the contacts on the top face of the spacerextending into the enclosure but being spaced from the extensions of thecontacts of the second plurality, the electrical connections being madewithin the enclosure to the extensions and to the first plurality of thecontacts where they extend into the enclosure, and a top layer ofinsulating material closing off the enclosure but not covering thecontacts on the top face of the spacer.
 5. A chip carrier according toclaim 4, characterised in that the top face of the spacer provides ashoulder running around the inside of the spacer on which shoulder islocated the top layer.
 6. A chip carrier comprising:a body of flatelectrically insulating material of rectangular external configurationdefining upper and lower major surfaces; a first plurality of electricalcontacts arranged side-by-side along the four sides of the upper surfaceand a second plurality of electrical contacts arranged side-by-sidealong the four sides of the lower surface, the contacts of the firstplurality being separate from the contacts of the second plurality; asingle chip mounted on the insulating material and completely enclosed;and electrical connections between the chip and the contacts, said chipcarrier in combination with at least one other similar said chipcarrier, the chip carriers being arranged side-by-side with each majorsurface of each chip carrier being parallel to and facing one of themajor surfaces of the adjacent chip carrier, the chip carriers beingspaced from each other by spacing means which makes electrical contactwith the contacts.
 7. A chip carrier according to claim 6, characterisedin that the spacing means comprises at least one continuous member madeof insulating material which has a plurality of side-by-side slots whicheach receive, support and locate an edge of a respective one of the chipcarriers, the slots incuding electrically conductive areas forconnecting to the contacts on the chip carriers.
 8. A chip carrieraccording to claim 7, characterised in that there are four suchcontinuous members each of whose slots receives, supports and locates arespective one of the four edges of a respective one of the chipcarriers.
 9. A chip carrier according to claim 6, characterised in thatthe spacing means comprises a plurality of individual spacers eachplaced between a respective pair of the chip carriers.
 10. An electriccircuit assembly, comprisinga plurality of individual chip carriers eachof which is in the form of a body of electrically insulating materialdefining and separating first and second opposed major surfaces eachcarrying a respective plurality of electrical contacts arranged adjacentto its periphery with the contacts of one plurality being separated fromthose of the other plurality, and having a single chip carried by theinsulating material and electrically connected to contacts of both saidpluralities, and mounting means mounting the chip carriers in stackedconfiguration so that one of the said major surfaces on one carrierfaces but is separated from a respective one of the major surfaces oneach adjacent carrier, the mounting means including a plurality ofspacing elements each of which is placed between the said facing majorsurfaces of a respective pair of adjacent chip carriers, each saidspacing element comprising electrically insulating material supporting aplurality of electrical contacts configured so as to connect torespective ones of the said contacts on the chip carriers.
 11. Anassembly according to claim 10, in which each spacing element defines agap of predetermined size extending between the said facing majorsurfaces of the respective pair of adjacent chip carriers, and includingelectrical connections extending across the gap and connectionrespective ones of the contcts supported on the spacing element.
 12. Anassembly according to claim 10, in which each spacing element haselectrical connections extending through it and connecting respectiveones of the contacts which it supports.
 13. An assembly according toclaim 10, in which each spacing element is in the form of a frame-shapedmember matching the peripheral shape of each chip carrier.
 14. Anassembly according to claim 13, in which each chip carrier is ofrectangular configuration with the electrically insulating materialbeing in the form of a unitary slab defining the opposed major surfaces.15. An assembly according to claim 14, in which each chip is mounted onone of the said surfaces of the respective slab and connected to thecontacts on the other said surface thereof by means of plated-throughholes extending through the slab.
 16. An assembly according to claim 14,in which each slab has an opening through it of greater size than therespective chip, the chip being mounted within the opening, andincluding electrical connections which connect the chip to the saidcontacts on the slab and which also physically support the chip withinthe opening.
 17. An assembly according to claim 13, in which theinsulating material of each chip carrier is in the form ofa squareunitary base slab one of whose major surfaces defines the said firstmajor surface and the other of which defines an intermediate surface,and having one said plurality of the contacts arranged along the fouredges of the said first surface but each such contact having anextension onto the said intermediate surface, a square hollowframe-shaped spacer of insulating material matching the size of the baseslab and defining frame-shaped top and under faces and having the othersaid plurality of contacts arranged along its top face, the spacer beingmounted with its said under face on the said intermediate surface of thebase slab so as to define an enclosure with that intermediate surfaceand in which enclosure the said chip is mounted, the spacer being sizedso that the said extensions of the contacts on the base slab extend intothe enclosure, and the contacts on the top face of the spacer extendinginto the enclosure but being spaced from the said extensions of thecontacts of the other plurality, and a top layer of insulating materialclosing off the enclosure but not covering the contacts on the top faceof the spacer, the top layer together with the top face of the spacerdefining the said second major surface.